This Application Note describes various Vectron clock sources and interface circuits that can be used to drive the Reference Clock (REFCLK) Inputs of the SerDes Blocks of the RTG4 radiation-tolerant FPGA.
The Microchip RTG4 (Radiation-Tolerant Generation4) FPGA (Field Programmable Gate Array) can receive clock signals in two types of clock inputs:
1. Clock signals into the RTG4 general purpose and dedicated clock input pins, for use as a clock to the logic in the Digital Fabric.
2. Clock signals into the SerDes Blocks Reference Clock input pins, which input a reference clock for use by the dedicated high-speed SerDes Blocks on chip.
|
DSC1103CE1-200.0000T |
DSC1103 |
200MHz |
|
DSC1103CE1-200.0000T |
DSC1103 |
200MHz |
|
DSC1103CE1-200.0000T |
DSC1103 |
200MHz |
|
DSC1103CE1-156.2500T |
DSC1103 |
156.25MHz |
|
DSC1103CE1-156.2500T |
DSC1103 |
156.25MHz |
|
DSC1103CE1-156.2500T |
DSC1103 |
156.25MHz |
|
DSC1122CI1-156.2500 |
DSC1122 |
156.25MHz |
|
DSC1123AE1-125.0000T |
DSC1123 |
125MHz |
|
DSC1123AE1-125.0000T |
DSC1123 |
125MHz |
|
DSC1123AE1-125.0000T |
DSC1123 |
125MHz |
|
DSC1122AE2-156.2500 |
DSC1122 |
156.25MHz |
|
DSC1122BE1-156.2500T |
DSC1122 |
156.25MHz |
|
DSC1122BE1-156.2500T |
DSC1122 |
156.25MHz |
|
DSC1122BE1-156.2500T |
DSC1122 |
156.25MHz |
|
DSC1123AE2-040.0000 |
DSC1123 |
40MHz |
|
DSC1123AI2-040.0000 |
DSC1123 |
40MHz |
|
DSC1122BI1-100.0000 |
DSC1122 |
100MHz |
|
DSC1122BI2-100.0000 |
DSC1122 |
100MHz |
|
DSC1122BI2-114.2850 |
DSC1122 |
114.285MHz |
|
DSC1122BI2-155.5200 |
DSC1122 |
155.52MHz |
|
DSC1122BI2-156.2500 |
DSC1122 |
156.25MHz |
|
DSC1102BI1-100.0000 |
DSC1102 |
100MHz |
|
DSC1122AI2-150.0000 |
DSC1122 |
150MHz |
|
DSC1001DL5-075.0000 |
DSC1001 |
75MHz |
|
DSC1001DL5-133.3330 |
DSC1001 |
133.333MHz |
|
DSC1101CM1-075.0000 |
DSC1101 |
75MHz |
|
DSC1101CM1-033.3333 |
DSC1101 |
33.3333MHz |
|
DSC1101CM1-005.0000 |
DSC1101 |
5MHz |
|
DSC1001DI5-080.0000 |
DSC1001 |
80MHz |
|
DSC1123CE5-100.0000 |
DSC1123 |
100MHz |
Of the two types of clock inputs, RTG4 REFCLK Inputs will be examined for this Application Note. The RTG4 REFCLK Inputs can be programmed by a FPGA designer to one of the various receiver types (differential or single-ended signal), and each has logic level requirements that will need direct interface or translation interface circuit connections to work properly when used with a standard clock driver (See Table 3). Information for providing clock input to the RTG4 Digital Fabric (type ‘1’ above) is not presented here, but it can be connected with a standard driver clock the same as providing clock input to the RTG4 REFCLK receivers.
|
DSC1122NI5-025.0020 |
DSC1122 |
25.002MHz |
|
DSC1103DI5-171.8181T |
DSC1103 |
171.8181MHz |
|
DSC1103DI5-171.8181T |
DSC1103 |
171.8181MHz |
|
DSC1103DI5-171.8181T |
DSC1103 |
171.8181MHz |
|
DSC1103DI5-171.8181 |
DSC1103 |
171.8181MHz |
|
DSC1102CI5-150.0000T |
DSC1102 |
150MHz |
|
DSC1102CI5-150.0000T |
DSC1102 |
150MHz |
|
DSC1102CI5-150.0000T |
DSC1102 |
150MHz |
|
DSC1103CI5-224.8200 |
DSC1103 |
224.82MHz |
|
DSC1123AL1-150.0000 |
DSC1123 |
150MHz |
|
DSC1122AI5-025.0020 |
DSC1122 |
25.002MHz |
|
DSC1123BI5-156.2500T |
DSC1123 |
156.25MHz |
|
DSC1123BI5-156.2500T |
DSC1123 |
156.25MHz |
|
DSC1123BI5-156.2500T |
DSC1123 |
156.25MHz |
|
DSC1103CL5-106.2500T |
DSC1103 |
106.25MHz |
|
DSC1103CL5-106.2500T |
DSC1103 |
106.25MHz |
|
DSC1103CL5-106.2500T |
DSC1103 |
106.25MHz |
|
DSC1124CI1-156.2500TA |
DSC1124 |
156.25MHz |
|
DSC1124CI1-156.2500TA |
DSC1124 |
156.25MHz |
|
DSC1124CI1-156.2500TA |
DSC1124 |
156.25MHz |
|
DSC1103BL5-062.5000 |
DSC1103 |
62.5MHz |
|
MX553BBA312M500 |
MX55 |
312.5MHz |
|
DSC6111CI1A-016.0000 |
DSC6100 |
16MHz |
|
DSC1001CL2-012.0000 |
DSC1001 |
12MHz |
|
DSC1001DI1-050.0000 |
DSC1001 |
50MHz |
|
DSC1001DI1-024.0000 |
DSC1001 |
24MHz |
|
DSC1001DI1-025.0000 |
DSC1001 |
25MHz |
|
DSC1001CI2-033.3300 |
DSC1001 |
33.33MHz |
|
DSC1001DI5-100.0000 |
DSC1001 |
100MHz |
|
DSC1001DL5-025.0000 |
DSC1001 |
25MHz |
In addition to listing and discussing these devices, this Application Note also summarizes the RTG4 REFCLK Inputs specification logic levels required for the clock source drivers with output logic levels presented in Table 3. The Application Note also shows setups and measurements with some typical waveforms tested in the RTG4 DevKit, to provide confidence that the solutions do work in hardware.
|
DSC1001CE2-006.0000 |
DSC1001 |
6MHz |
|
DSC1001CI1-050.0000 |
DSC1001 |
50MHz |
|
DSC1001CI2-012.0000 |
DSC1001 |
12MHz |
|
DSC1001CI2-033.3333 |
DSC1001 |
33.3333MHz |
|
DSC1001CI5-004.9152 |
DSC1001 |
4.9152MHz |
|
DSC1122CI5-200.0000 |
DSC1122 |
200MHz |
|
DSC1001CI1-048.0000 |
DSC1001 |
48MHz |
|
DSC1001CI1-026.0000 |
DSC1001 |
26MHz |
|
DSC1001AI2-050.0000 |
DSC1001 |
50MHz |
|
DSC1001AL2-027.0000 |
DSC1001 |
27MHz |
|
DSC6083HE1A-032K800T |
DSC60XX |
32.8kHz |
|
DSC6083HE1A-032K800T |
DSC60XX |
32.8kHz |
|
DSC6083HE1A-032K800T |
DSC60XX |
32.8kHz |
|
DSC6011HI1A-002.5000T |
DSC60XX |
2.5MHz |
|
DSC6011HI1A-002.5000T |
DSC60XX |
2.5MHz |
|
DSC6011HI1A-002.5000T |
DSC60XX |
2.5MHz |
|
DSC6013HI1A-002.5000T |
DSC60XX |
2.5MHz |
|
DSC6013HI1A-002.5000T |
DSC60XX |
2.5MHz |
|
DSC6013HI1A-002.5000T |
DSC60XX |
2.5MHz |
|
DSC6083HI2A-002K000T |
DSC60XX |
2kHz |
|
DSC6083HI2A-002K000T |
DSC60XX |
2kHz |
|
DSC6083HI2A-002K000T |
DSC60XX |
2kHz |
|
DSC6083CI2A-032K768 |
DSC60XX |
32.768kHz |
|
DSC6001CI2A-016.0000 |
DSC60XX |
16MHz |
|
DSC6003CI2A-012.0000 |
DSC60XX |
12MHz |
|
DSC6003CI2A-024.0000 |
DSC60XX |
24MHz |
|
DSC6003CI2A-016.0000 |
DSC60XX |
16MHz |
|
DSC6101CI2A-027.0000 |
DSC6100 |
27MHz |
|
DSC6111CI2A-012.0000 |
DSC6100 |
12MHz |
|
DSC6102CI2A-100.0000 |
DSC6100 |
100MHz |
本应用笔记描述了可用于驱动 RTG4 耐辐射 FPGA 的 SerDes ?？榈牟慰际敝?(REFCLK) 输入的各种 Vectron 时钟源和接口电路。
Microchip RTG4 (Radiation-Tolerant Generation4) FPGA (Field Programmable Gate Array) 可以在两种类型的时钟输入中接收时钟信号：
1. 时钟信号进入 RTG4 通用和专用时钟输入引脚，用作数字结构中逻辑的时钟。
2. 时钟信号进入 SerDes ?？椴慰际敝邮淙牍芙?，该管脚输入参考时钟，供片上专用高速 SerDes ?？槭褂?。
|
DSC6101CI2A-050.0000 |
DSC6100 |
50MHz |
|
DSC6101CI2A-025.0000 |
DSC6100 |
25MHz |
|
DSC6003JI2A-048.0000 |
DSC60XX |
48MHz |
|
DSC6101JI2A-026.0000 |
DSC6100 |
26MHz |
|
DSC6101JI2A-048.0000 |
DSC6100 |
48MHz |
|
DSC6003JI2A-016.0000 |
DSC60XX |
16MHz |
|
DSC6101JI2A-012.2880 |
DSC6100 |
12.288MHz |
|
DSC6101JI2A-050.0000 |
DSC6100 |
50MHz |
|
DSC6102JI2A-100.0000 |
DSC6100 |
100MHz |
|
DSC6111JI2A-024.0000 |
DSC6100 |
24MHz |
|
DSC6101JI2A-012.0000 |
DSC6100 |
12MHz |
|
DSC6101JI2A-027.0000 |
DSC6100 |
27MHz |
|
DSC1121CI2-050.0000 |
DSC1121 |
50MHz |
|
DSC1121CI2-025.0000 |
DSC1121 |
25MHz |
|
DSC1121BI2-025.0007 |
DSC1121 |
25.0007MHz |
|
DSC1121AE2-025.0000 |
DSC1121 |
25MHz |
|
DSC1101CI1-025.0000 |
DSC1101 |
25MHz |
|
DSC1001CC1-008.0000 |
DSC1001 |
8MHz |
|
DSC1101DL1-027.0000 |
DSC1101 |
27MHz |
|
DSC1001CE1-066.6666 |
DSC1001 |
66.6666MHz |
|
DSC1001CE1-019.2000 |
DSC1001 |
19.2MHz |
|
DSC1033CE2-022.5792 |
DSC1033 |
22.5792MHz |
|
DSC1001DI1-004.9152 |
DSC1001 |
4.9152MHz |
|
DSC1033AE1-024.0000 |
DSC1033 |
24MHz |
|
DSC1001AC1-027.0000 |
DSC1001 |
27MHz |
|
DSC1033CE2-074.2500 |
DSC1033 |
74.25MHz |
|
DSC1033BE1-050.0000 |
DSC1033 |
50MHz |
|
DSC1001AC1-008.0000 |
DSC1001 |
8MHz |
|
DSC1033DI1-048.0000 |
DSC1033 |
48MHz |
|
DSC1001DI1-012.0000 |
DSC1001 |
12MHz |
在这两种类型的时钟输入中，RTG4 REFCLK 输入将在本应用笔记中进行检查。 RTG4 REFCLK 输入可由 FPGA 设计人员编程为各种接收器类型之一（差分或单端信号），并且每个都具有逻辑电平要求，需要直接接口或转换接口电路连接才能在与标准时钟驱动器。此处未介绍为 RTG4 数字结构（上述类型“1”）提供时钟输入的信息，但它可以与标准驱动器时钟连接，就像为 RTG4 REFCLK 接收器提供时钟输入一样。
|
DSC1001DI1-048.0000 |
DSC1001 |
48MHz |
|
DSC1033DI1-064.0000 |
DSC1033 |
64MHz |
|
DSC1033DI1-025.0000 |
DSC1033 |
25MHz |
|
DSC1033CI1-008.1920 |
DSC1033 |
8.192MHz |
|
DSC1033DI1-050.0000 |
DSC1033 |
50MHz |
|
DSC1033DI1-024.0000 |
DSC1033 |
24MHz |
|
DSC1033DI1-016.0000 |
DSC1033 |
16MHz |
|
DSC1001DI1-020.0000 |
DSC1001 |
20MHz |
|
DSC1001CI1-025.0000 |
DSC1001 |
25MHz |
|
DSC1033BI2-027.1200 |
DSC1033 |
27.12MHz |
|
DSC1001DI1-032.0000 |
DSC1001 |
32MHz |
|
DSC1033DI1-029.4912 |
DSC1033 |
29.4912MHz |
|
DSC1001AE1-027.0000 |
DSC1001 |
27MHz |
|
DSC1001AE1-014.3182 |
DSC1001 |
14.3182MHz |
|
DSC1001AE1-024.5761 |
DSC1001 |
24.5761MHz |
|
DSC1001AE1-054.0000 |
DSC1001 |
54MHz |
|
DSC1001AE1-003.6864 |
DSC1001 |
3.6864MHz |
|
DSC1001BE2-010.0000 |
DSC1001 |
10MHz |
|
DSC1001AE1-055.0000 |
DSC1001 |
55MHz |
|
DSC1033CI1-001.0000 |
DSC1033 |
1MHz |
|
DSC1004AI2-001.0000 |
DSC1004 |
1MHz |
|
DSC1001CI1-003.6864 |
DSC1001 |
3.6864MHz |
|
DSC1001DI1-038.4000 |
DSC1001 |
38.4MHz |
|
DSC1001AI2-064.0000 |
DSC1001 |
64MHz |
|
DSC1001BI1-048.0000 |
DSC1001 |
48MHz |
|
DSC1001CI2-001.9521 |
DSC1001 |
1.9521MHz |
|
DSC1001CI2-010.4857 |
DSC1001 |
10.4857MHz |
|
DSC1001CI2-008.1920 |
DSC1001 |
8.192MHz |
|
DSC1001AI1-033.0000 |
DSC1001 |
33MHz |
|
DSC1001BI1-010.0000 |
DSC1001 |
10MHz |
除了列出和讨论这些器件外，本应用笔记还总结了时钟源驱动器所需的 RTG4 REFCLK 输入规范逻辑电平，输出逻辑电平应用笔记还展示了一些典型波形的设置和测量，在RTG4 DevKit，提供解决方案在硬件中工作的信心。
|
DSC1001BI1-020.0000 |
DSC1001 |
20MHz |
|
DSC1001BI1-024.5760 |
DSC1001 |
24.576MHz |
|
DSC1001BI1-027.0000 |
DSC1001 |
27MHz |
|
DSC1001BI2-014.3181 |
DSC1001 |
14.3181MHz |
|
DSC1001BI2-014.7456 |
DSC1001 |
14.7456MHz |
|
DSC1001BI2-016.3840 |
DSC1001 |
16.384MHz |
|
DSC1001BI2-040.0000 |
DSC1001 |
40MHz |
|
DSC1001AI2-001.0000 |
DSC1001 |
1MHz |
|
DSC1001BI1-024.0000 |
DSC1001 |
24MHz |
|
DSC1001BI1-025.0000 |
DSC1001 |
25MHz |
|
DSC1001BI2-012.5000 |
DSC1001 |
12.5MHz |
|
DSC1001BI1-040.0000 |
DSC1001 |
40MHz |
|
DSC1001BI1-050.0000 |
DSC1001 |
50MHz |
|
DSC1001BI2-024.5760 |
DSC1001 |
24.576MHz |
|
DSC1003DI2-100.0000 |
DSC1003 |
100MHz |
|
DSC1033BI1-025.0000 |
DSC1033 |
25MHz |
|
DSC1001BI2-005.5296 |
DSC1001 |
5.5296MHz |
|
DSC1001CI2-049.1520 |
DSC1001 |
49.152MHz |
|
DSC1001BI2-025.0000 |
DSC1001 |
25MHz |
|
DSC1001CI2-025.0000 |
DSC1001 |
25MHz |
|
DSC1001CE2-012.0000 |
DSC1001 |
12MHz |
|
DSC1001DI2-045.1584 |
DSC1001 |
45.1584MHz |
|
DSC1001DI2-049.1520 |
DSC1001 |
49.152MHz |
|
DSC1001DI2-011.0592 |
DSC1001 |
11.0592MHz |
|
DSC1001AE2-002.0480 |
DSC1001 |
2.048MHz |
|
DSC1001CI2-001.9512 |
DSC1001 |
1.9512MHz |
|
DSC1001CI2-033.3330 |
DSC1001 |
33.333MHz |
|
DSC1001DL1-025.2000 |
DSC1001 |
25.2MHz |
|
DSC1121CM1-024.0000 |
DSC1121 |
24MHz |
|
DSC1121CM1-050.0000 |
DSC1121 |
50MHz |
CLOCKS FOR DRIVING RTG4 FPGA REFCLK INPUTS
The following Vectron differential signal crystal oscillators are recommended for use with the RTG4 FPGA REFCLK receivers:
• LVDS
- DOC203679, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, LVDS Output
- DOC206903, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, 300krad Tolerant, LVDS Output
• LVPECL
- DOC203810, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, LVPECL Output
• CMOS
- OS-68338, Oscillator Specification, Hybrid Clock, Hi-Rel Standard, CMOS Output (3.3V supply, 100krad)
- DOC206379, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, 300krad Tolerant CMOS (3.3V supply, 300krad)
- DOC204900, Oscillator Specification, Hybrid Clock for Hi-Rel Standard, High Frequency CMOS (2.5V/3.3V supply, 100krad)
|
DSC1001BI2-004.0000 |
DSC1001 |
4MHz |
|
DSC1001BI2-010.0000 |
DSC1001 |
10MHz |
|
DSC1001BI2-013.0810 |
DSC1001 |
13.081MHz |
|
DSC1001BI2-054.0000 |
DSC1001 |
54MHz |
|
DSC1001AI2-011.7000 |
DSC1001 |
11.7MHz |
|
DSC1001AI2-012.3667 |
DSC1001 |
12.3667MHz |
|
DSC1001CL1-016.0000 |
DSC1001 |
16MHz |
|
DSC1003CI2-050.0000 |
DSC1003 |
50MHz |
|
DSC1001CL1-033.3333 |
DSC1001 |
33.3333MHz |
|
DSC1001BI2-012.2888 |
DSC1001 |
12.2888MHz |
|
DSC1124CE1-010.2400 |
DSC1124 |
10.24MHz |
|
DSC1001CI2-150.0000 |
DSC1001 |
150MHz |
|
DSC1001BL1-060.0000 |
DSC1001 |
60MHz |
|
DSC1101DM1-012.0000 |
DSC1101 |
12MHz |
|
DSC1001DI2-005.0196 |
DSC1001 |
5.0196MHz |
|
DSC1001CI5-019.2000 |
DSC1001 |
19.2MHz |
|
DSC1001CI5-009.6000 |
DSC1001 |
9.6MHz |
|
DSC1001CI5-009.7280 |
DSC1001 |
9.728MHz |
|
DSC1001DL2-016.0000 |
DSC1001 |
16MHz |
|
DSC1033DI1-080.0000 |
DSC1033 |
80MHz |
|
DSC1001CI5-016.3840 |
DSC1001 |
16.384MHz |
|
DSC1001BE1-125.0000 |
DSC1001 |
125MHz |
|
DSC1001CI5-060.0000 |
DSC1001 |
60MHz |
|
DSC1004DI2-010.0000 |
DSC1004 |
10MHz |
|
DSC1001DI1-012.8000 |
DSC1001 |
12.8MHz |
|
DSC1004DI2-016.0000 |
DSC1004 |
16MHz |
|
DSC1001DI2-028.6363 |
DSC1001 |
28.6363MHz |
|
DSC1001CI5-026.0000 |
DSC1001 |
26MHz |
|
DSC1001DI2-031.2500 |
DSC1001 |
31.25MHz |
|
DSC1001DI2-037.1250 |
DSC1001 |
37.125MHz |
用于驱动 RTG4 FPGA REFCLK 输入的时钟
建议将以下 Vectron 差分信号晶体振荡器与 RTG4 FPGA REFCLK 接收器一起使用：
• LVDS
- DOC203679，
振荡器规范，用于 Hi-Rel 标准的混合时钟，LVDS 输出
- DOC206903，振荡器规范，用于 Hi-Rel 标准的混合时钟，300krad 容差，LVDS 输出
• LVPECL
- DOC203810，振荡器规范，用于 Hi-Rel 标准的混合时钟，LVPECL 输出
• CMOS
- OS-68338，振荡器规格，混合时钟，Hi-Rel 标准，CMOS 输出（3.3V 电源，100krad）
- DOC206379，振荡器规范，用于 Hi-Rel 标准的混合时钟，300krad 容限 CMOS（3.3V 电源，300krad）
- DOC204900，振荡器规范，用于 Hi-Rel 标准的混合时钟，高频 CMOS（2.5V/3.3V 电源，100krad）
|
DSC1001CI5-032.0000 |
DSC1001 |
32MHz |
|
DSC1001DI2-024.0000 |
DSC1001 |
24MHz |
|
DSC1001DI2-050.0000 |
DSC1001 |
50MHz |
|
DSC1001DI2-029.5000 |
DSC1001 |
29.5MHz |
|
DSC1001DI2-027.0000 |
DSC1001 |
27MHz |
|
DSC1121DI2-125.0000 |
DSC1121 |
125MHz |
|
DSC1001CL2-030.0000 |
DSC1001 |
30MHz |
|
DSC1003DL5-020.0000 |
DSC1003 |
20MHz |
|
DSC1003DL5-025.0000 |
DSC1003 |
25MHz |
|
DSC1030CI1-026.0000 |
DSC1030 |
26MHz |
|
DSC1001BL2-020.0000 |
DSC1001 |
20MHz |
|
DSC1001AE1-111.0000 |
DSC1001 |
111MHz |
|
DSC1001CL5-014.3181 |
DSC1001 |
14.318MHz |
|
DSC1001CL5-010.0000 |
DSC1001 |
10MHz |
|
DSC1001AI2-096.0000 |
DSC1001 |
96MHz |
|
DSC1001AI2-100.0000 |
DSC1001 |
100MHz |
|
DSC1001BI2-125.0000 |
DSC1001 |
125MHz |
|
DSC1001CI5-024.3050 |
DSC1001 |
24.305MHz |
|
DSC1001CI5-033.3300 |
DSC1001 |
33.33MHz |
|
DSC1001AE5-040.0000 |
DSC1001 |
40MHz |
|
DSC1001BE5-064.0000 |
DSC1001 |
64MHz |
|
DSC1124BI1-100.0000 |
DSC1124 |
100MHz |
|
DSC1001DL2-030.0000 |
DSC1001 |
30MHz |
|
DSC1001DL2-027.0000 |
DSC1001 |
27MHz |
|
DSC1001DL2-013.5000 |
DSC1001 |
13.5MHz |
|
DSC1001AI5-027.0000 |
DSC1001 |
27MHz |
|
DSC1001AI5-033.0000 |
DSC1001 |
33MHz |
|
DSC1001BI5-013.5600 |
DSC1001 |
13.56MHz |
|
DSC1001BI5-040.0000 |
DSC1001 |
40MHz |
|
DSC1001CE5-148.0000 |
DSC1001 |
148MHz |
销售代表
